update img

user_guide/README.md

@@ -8,5 +8,5 @@ A typical design flow consists of creating a Vivado(ISE) project, creating model
 
 ## FPGAOL DEV BOARD schematic diagram
 
-![](img/board.svg)
+![](img/fpgaol_board.png)
 

user_guide/ch2.md

@@ -20,19 +20,19 @@ Press **select file** button to select your bitstream file.
 
 ![bitstream](img/bitstream.png)
 
-Then, press **Program** button to upload and program your bistream file. It will take approximately 10 Secs to upload and program.
+Then, press **Program** button to upload and program your bitstream file. It will take approximately 10 Secs to upload and program.
 
 ![progsuccess](img/progsuccess.png)
 
 ### use human interface
 
-After the bistream file is successfully uploaded and programmed, you can gain access to human interface to test your design. The behavor depends on your design.
+After the bistream file is successfully uploaded and programmed, you can gain access to FPGA interface to test your design. The behavor depends on your design.
 
 ![interface](img/interface.png)
 
 ### use waveform
 
-Sample-based waveform chart is provided. 
+Sample-based waveform chart is provided.
 
 ![waveform](img/waveform.png)