# FPGAOL user guide

This tutorial guides you through the design flow using Xilinx software to create a project and testing on FPGAOL. 

A typical design flow consists of creating a Vivado(ISE) project, creating model(s), assigning FPGAOL constraint file(s), optionally running behavioral simulation,  generating the bitstream, and finally verifying the functionality on FPGAOL website.

![design flow](img/design_flow.png)

## FPGAOL DEV BOARD schematic diagram

<img src="img/board.svg" alt="scheme" style="zoom:150%;" />