页-1
CFF Container
工作表.36
工作表.37
design flow
design flow
Swimlane List
Swimlane
工作表.40
工作表.41
simulate
simulate
Swimlane.9
工作表.43
工作表.44
design
design
Swimlane.15
工作表.46
工作表.47
test
test
Phase List
Separator
工作表.50
工作表.51
Start/End
start
start
Process
Creating a Vivado project
Creating a Vivado project
Process.48
creating models
creating models
Dynamic connector
Start/End.66
finish
finish
流程.110
assigning FPGAOL constraint files
assigning FPGAOL constraint files
动态连接线.111
流程.112
generating the bitstream
generating the bitstream
流程.113
testing on FPGAOL
testing on FPGAOL
流程.114
Simulation
Simulation
动态连接线.115
动态连接线.117
动态连接线.118
动态连接线.119
N
N
动态连接线.121
Y
Y
判定
Result correct?
Result correct?
判定.122
Result correct?
Result correct?
动态连接线.123
动态连接线.124
y
y
动态连接线.125
N
N
动态连接线.126