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README.md

FPGAOL user guide

This tutorial guides you through the design flow using Xilinx software to create a project and testing on FPGAOL.

A typical design flow consists of creating a Vivado(ISE) project, creating model(s), assigning FPGAOL constraint file(s), optionally running behavioral simulation, generating the bitstream, and finally verifying the functionality on FPGAOL website.

design flow

FPGAOL DEV BOARD schematic diagram

scheme